----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:44:59 04/22/2010 
-- Design Name: 
-- Module Name:    ad8020_clk_divider - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ad8020_clk_divider is
    Port ( clk_in : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end ad8020_clk_divider;

architecture Behavioral of ad8020_clk_divider is

begin

P1: process(clk_in)
variable counter : STD_LOGIC_VECTOR (4 downto 0) := "00000";
begin

if rising_edge(clk_in) then 

	
	if counter = "01110" then clk_out <= '1' ;
	elsif counter = "11100" then clk_out <= '0'; counter := "00000";
	end if;
	counter := counter + "1";
end if;

end process;

end Behavioral;

